Topic       : Pure Assembler Documentation
Author      : John Kormylo
Version     : PASM.HYP 1.0
Subject     : Documentation/Pure Assembler
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HCP-Version : 3
Compiled on : Atari
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View Ref-File[ Paged Memory Management ]

... is used to implement virtual memory systems or to prevent one
application in a multi-tasking environment from interfering with
another.  PMMU instructions are primarily of interest to designers
of operating systems.

The idea is that the address used by a program can be different than
the physical address in RAM.  The Address Translation Cache (ATC)
is a table kept in RAM which is used to translate effective addresses
into physical addresses.  The highest n bits in the address are
added to a root pointer to locate a table entry, which then points to
another table.  The next highest n bits in the address are added to
this address to locate the next table entry, and so on until the last
table entry which points to a RAM page.  The remaining bits are added
to this address and the memory access is performed.

The 68030 uses six additional registers to perform PMMU functions:

Supervisor Root Pointer  SRP      64 bits
CPU Root Pointer         CRP      64 bits
Translation Control      TC       32 bits
PMMU Status Register     PSR      16 bits
Transparent Translation  TT0/TT1  32 bits each

The SRP and CRP point to the ATCs in RAM for Supervisor Mode and
User Mode, respectively.  The TC determines how many levels to use
and how many bits per level.  The PSR is set by the PTEST instruction
to test memory access.  TT0 and TT1 allow direct access to 16 MBytes
(or more) with no translation.

TOS has the PMMU turned off (see TC).