Topic       : Pure Assembler Documentation
Author      : John Kormylo
Version     : PASM.HYP 1.0
Subject     : Documentation/Pure Assembler
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Compiled on : Atari
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View Ref-File[ Memory Cache ]

... is a FIFO (First In, First Out) buffer to speed up memory access.
If the desired item is already in the cache (a cache hit), it can be
read faster than from RAM.  In burst mode, RAM access can run
concurrently with CPU operations.

The 68030 has 512 bytes of internal memory for cache storage; 256 for
data and 256 for instructions.  These are divided into 16 groups of 4
longwords each.  In burst mode, each RAM access reads in 4 longwords
aligned to a 16 byte boundary, starting with the desired address then
filling in the remaining addresses in the 16 byte block.  In normal
mode only the needed addresses (aligned to a 4 byte boundary) are read
in.  If the item extends over two (aligned) longwords, both will be
read in.

All write operations go both to RAM and the cache (on a hit), so that
later reads will be correct whether from RAM or the cache.  Write
Allocation (when turned on) means that the cache will be filled (on a
miss) by write accesses as well as by read access, provided that the
destination is a properly aligned longword.

The one drawback with caching is that when other chips modify RAM
contents, these changes will not show up in the cache.

See also CACR and CAAR.