Topic : CTPCI Documentation Author : Sascha Uhlig (Editor) Version : CTPCI.hyp (5/12/2010) Subject : Expansion Card Nodes : 135 Index Size : 3892 HCP-Version : 5 Compiled on : Atari @charset : atarist @lang : @default : Title Page @help : Help Page @options : -i +zz @width : 70 View Ref-FileC.12 PCI 9054 Errata CTPCI In the following, you will find edited excerpts from the errata documentation PCI 9054AC Errata, revision 1.7 from May 2005, for the PCI 9054 Silicon Revision AC used on the CTPCI. 2. Simultaneous Access to Queue Register in Messaging Unit Erratum Issue: The PCI 9054 updates one of four queue pointers automatically each time there is a read or write to the messaging unit Inbound (Port 40h) or Outbound (Port 44h) ports. The four registers are the Inbound Free Tail Pointer (IFTPR), the Inbound Post Head Pointer (IPHPR), the Outbound Free Head Pointer (OFHPR) and Outbound Post Tail Pointer (OPTPR). If a local master initiates a write to the PCI 9054 messaging unit queue registers simultaneous to a PCI access to the Inbound or Outbound ports, the PCI 9054 will fail to automatically increment the appropriate pointers to reflect this. This can result in overwriting a previous message or retrieving a previously read message from the queue. These pointers cannot be 'corrected' due to the fact that the IOP cannot determine if an increment failure has occurred. The failure only occurs when the PCI 9054 returns READY#/TA# to the local master simultaneous with the PCI 9054 returning TRDY# to the PCI master on an Inbound or Outbound port access that has been retried. This erratum does not affect the I2O protocol. It only affects custom messaging unit implementations. Solutions/Workarounds (use any): 1. Disable the PCI r2.1 Features Enable bit by clearing MARBR[24]. With this bit clear, the PCI Target Retry Delay Clocks register bits (LBRD0[31:28]) should be set to a value of 3h or greater. 2. For multiple initiator implementations: a. Implement a semaphore using two on-chip mailboxes or any shared memory region, so that the local master can access the messaging unit queue registers only when the PCI master is not accessing them. Use one mailbox to signal that the PCI bus wants to access the messaging unit and the other mailbox to signal that the local bus wants to access the messaging unit. Before accessing the messaging unit read the status of the opposite side's mailbox. If the other side has access then back off (attempt access later) or else write a flag in the mailbox to claim access. Then read the other mailbox to ensure that both the PCI and local sides did not write their flags simultaneously. If they did, each side will need to back off, otherwise access the messaging unit and then clear the flag in the mailbox. b. Update the interfering queue registers only from the PCI side, via messages passed through the PCI 9054 internal mailbox registers. For single initiator implementations: Implement a single request/reply message protocol for custom message passing. This is recommended for applications where there is a single host and the host waits for a reply before initiating a new request. 3. Direct Master Read with PCI Initiator Cache Enabled Erratum Issue: PCI 9054 PCI Initiator (Direct Master) reads with PCI Initiator Cache enabled (DMPBAM[2] = 1) will result in 32-bit data reads intermittently returning incorrect data. The incorrect data returned will be the Lword value at the 32-bit aligned address that immediately precedes the correct value. In other words, data that has been previously cached and read out of the PCI Initiator Read FIFO will be repeated on a subsequent read. This erratum occurs in all three local bus modes (C, J and M). Solution/Workaround: Disable PCI Initiator Cache by clearing the PCI Initiator Cache Enable bit (DMPBAM[2] = 0). 5. Cannot Perform a New Read or Write after Backoff - Must Resume with Last Address Erratum Issue: The PCI 9054 Data Book version 2.1 pages 3-16 and 5-14 states: 'A new ... read is performed if the resumed Local Bus cycle is not the same as the Backed Off cycle'. When the PCI 9054 BREQo/ RETRY# signal is enabled (EROMBA[4] = 1) to back off a Direct Master transaction (to resolve a potential deadlock), if the local master does not resume a backed-off transfer with the originally backed-off address, the PCI 9054 will incorrectly assert BREQo/RETRY# without asserting LHOLD. If the local master does not apply the correct continuation address, BREQo/RETRY# will be asserted without LHOLD two clocks after the local master asserts ADS#. Solution/Workaround: Only resume a backed-off transfer with the continuation address, that is, the master must resume the backed-off transfer with the address that it was backed off from. 6. TEA# Pin/Signal Can Be Asserted Improperly General Functional Description of Proper TEA# Assertion: TEA#, Transfer Error Acknowledge, is a wired-OR signal that is asserted by a slave device on the local bus. The CT60/63 can assert TEA# as a master or slave if its bus monitor times out. If the bus monitor does time out and the CT60/63 asserts TEA#, the device it is communicating with needs to detect this regardless of its configuration (master or slave) and get off the local bus in one clock cycle. Additionally the device should terminate any active PCI bus activity via an abort and set its status bits/registers appropriately. Item #1 Erratum Issue:: The CT60/63 can assert TEA# as a master or slave if its bus monitor times out. 1. If TEA# is asserted by the CT60/63 while the PCI 9054AC is the local bus master, TEA# will preempt TA# input and terminate the current cycle. If the burst is not completed, the PCI 9054AC will generate a new TS# and continue. This applies for Direct Slave and DMA transfers. This case is possible if the PCI 9054 accesses on the CT60/63 at an address (bad) where there is no hardware answering (-> bus error). 2. If TEA# is asserted by the CT60/63 while the PCI 9054AC is the local bus slave, the PCI 9054AC ignores TEA#. This second case may only be possible if the CT60/63 watchdog reaches the 32us delay during an access from 060 to the PCI 9054. Solutions/Workarounds (use either): 1. Disable or program the processor bus monitor to a value high enough so that it exceeds the amount of time necessary to get the bus and execute the transfer. This feature is not possible on the CT60/63. The delay is hardware-fixed to 32us. 2. Have the processor assert the LINT# pin instead of TEA# when the bus monitor times out. That will cause the PCI INTA# interrupt pin to assert so that the system can issue a software reset to the local section, by setting the PCI 9054AC CNTRL register bit [30] to 1, and then clearing it after the reset is completed. This feature is currently not present on the CT60/ 63. It may be possible but needs to modify the SDR chip on the CT60/63. Item #2 Erratum Issue: If a Target Abort is received on any transfer, the PCI 9054AC may continue to drive the LD[0:31] pins for up to four cycles after TEA# has been asserted. Solution/Workaround: Do not start a new local bus cycle for at least four clocks after the PCI 9054AC asserts TEA#. Note: to be verified for the CTPCI! Item #3 Erratum Issue: TEA# will be improperly asserted by the PCI 9054AC if it is not participating in a local bus transfer if the two events listed below occur in the following sequence. 1. The BI# (Burst Inhibit) pin is asserted during a Direct Master or IDMA transfer. 2. A PCI Master/Target Abort is detected by the 9054AC when it is not participating in a local bus transfer. Solutions/Workarounds (use either): 1. Do not assert the BI# pin during a Direct Master or IDMA transfer. 2. Use the LINT# pin instead of the TEA# pin. Note: TEA# must be filtered if no access is started by the PCI 9054 on the local bus. 10. DMA Scatter/Gather Descriptor IRDY# PCI Protocol Violation Erratum issue: If the PCI 9054 receives a PCI Target Abort when reading a Scatter/Gather DMA descriptor from the PCI bus, the PCI 9054 will immediately float the IRDY# signal, rather than drive the IRDY# signal from active (level 0) to inactive (level 1) for one PCI clock period before floating, as is required by the PCI specification for STS I/O buffer protocol. As a result, it may take several PCI clocks for the IRDY# signal to reach a TTL logic level high. Solution/Workaround: No fix is required, and no failures have been observed. The PCI specification also requires that IDRY# have a pull-up resistor on the motherboard. If the above condition is encountered, adding an external pull-up (in parallel with motherboard pull-up) will decrease the resistance to allow the signal to reach a TTL logic high more quickly. 11. PQFP Package LA[0:5] Signal Noise Note: This erratum only pertains to the PQFP packaged PCI 9054AC part (PLX part number PCI 9054-AC50PI). It does not pertain to the PBGA packaged part (PLX part number PCI 9054-AC50BI). Erratum Issue: For the PCI 9054-AC50PI, noise may be injected on the local bus causing incorrect values to be output on address bits LA[0:5] if the following occur simultaneously: 1. The PCI 9054-AC50PI is driving the PCI bus with patterns that maximise the number of simultaneously switching outputs on AD[31:0], and 2. the PCI 9054-AC50PI is driving a local bus address during Direct Slave or DMA data transfers. The local bus signals affected LA[0:5] that should be logic 0s might be incorrectly driven to up to 0.8V for as long as 5ns. The amplitude of the noise is proportional to the loading and signal amplitude/ charge on the PCI AD[5:0] signals when these are driven low by the PCI 9054. Additionally, only local bus devices that detect a logic one near the bottom of the switching range are affected. Solutions/Workarounds (do one of the following): 1. Do not use the PCI 9054-AC50PI LA[0:5] signals in designs that perform Direct Slave or DMA data transfers. This will limit PCI 9054-AC50PI designs to the lower 64 Mbytes of local bus address space. 2. Use the PCI 9054-AC50BI or PCI 9056BA66BI parts instead which do not have this issue. 15. Direct Slave Disconnect without Data Erratum issue: When the PCI 2.2 Mode bit is set (MARBR[24] = 1), during a Direct Slave burst read, if the first datum is not available for transfer within 16 PCI clocks, the PCI 9054 will issue a PCI Retry, and latch the PCI Command, Address and Byte Enables into its Read FIFO. A PCI master that is target terminated with Retry must unconditionally repeat the same request until it completes. If instead at least one datum is transferred to the PCI bus, and if the next datum for the PCI burst read is not available within 8 PCI clocks, the PCI 9054 will issue a Disconnect Without Data (TRDY# de- asserted and STOP# asserted, same as Retry signalling). A PCI master that is target terminated with Disconnect is not required to repeat the same request. The PCI 9054 latches the Command, Address and Byte Enables into its Read FIFO and does not flush the FIFO when issuing a Disconnect Without Data, the same as it does when issuing a Retry (which is a special case of Disconnect Without Data). Therefore, the PCI 9054 requires that the PCI master repeat any transaction that the PCI 9054 terminates with a Disconnect Without Data. If a PCI master does not complete its originally requested Direct Slave Delayed Read transfer, the PCI 9054 flushes the Direct Slave Read FIFO after 2^15 PCI clocks and will grant an access to a new Direct Slave Read access. The PCI 9054 retries all other Direct Slave Read accesses that occur before the 2^15 PCI Clock timeout. Typically, if a PCI master receives a Disconnect Without Data in response to its issuance of a read command, the master will repeat the transaction (because the master still wants the data), and the PCI 9054 will respond normally. A situation in which a PCI master might instead read a different address would be an upstream bridge that is 64-bit architecture receiving the Disconnect Without Data on a non-Qword aligned address, with the PCI 9054 local address space being read mapped as prefetchable (the space's LASxRR[3] and PCIBAR[3] register bits are set). In this case, the bridge might repeat the read starting one address earlier, discarding the last Lword that it read in order to align its repeated read to a Qword- aligned address. The bridge is permitted to discard data only if the target's address space is mapped as prefetchable memory (LASxRR[3,0] = 10b). It is legal for a bridge to not discard the data but repeat the read starting with the Qword-aligned address with all Byte Enables de-asserted, however, such behaviour by design is unlikely. This erratum does not occur for reads of PCI 9054 registers, and is unlikely to occur for I/O-mapped local address spaces since typical CPUs do not perform burst I/O reads (a Disconnect Without Data can only occur on Burst transfers). Workaround: Configure memory-mapped local address spaces as non-prefetchable (LASxRR[3] = 0 in the serial EEPROM). Changing prefetchable mapping to non-prefetchable may reduce performance, since the upstream bridge is no longer allowed to prefetch beyond the amount of data that it was commanded to fetch.