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Topic       : Chips 'n Chips
Author      : Michael Ruge
Version     : chips_x.hyp (01/05/2001)
Subject     : Dokumentation/Hardware
Nodes       : 1505
Index Size  : 35662
HCP-Version : 3
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i -s +zz -t4
@width      : 75
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   What's the Difference Between 1K, 2K and 4K Refresh?

   Introduction
   DRAM refresh is a topic often misunderstood due to the many ways re-
   fresh can be accomplished. This article addresses the most often 
   asked question about the difference between 1K, 2K and 4K DRAMs.
 
   The Joint Electronics Design Engineering Council (JEDEC) has two 
   approved refresh types for 4MEG by x DRAMs. For example, one of 
   these JEDEC versions for a 4M x 4 DRAM requires 12 row-address bits
   and 10 column-address bits for 4,096 (4K) cycle refresh in 64ms.
   The next, for the same capacity DRAM, requires 11 row-address bits
   and 11 column-address bits for 2,048 (2K) cycle refresh in 32ms. 
   The last, for the same capacity DRAM, for 1,024 (1K) cycle refresh
   in 16ms. Except for this addressing difference, the performance of
   the DRAMs is the same.
 
   Why Three Types of Refresh?
   The main reason behind the addition of the 4K refresh version is de-
   creased power consumption. A DRAM device with 4K refresh draws less 
   current than the same capacity DRAM with 2K refresh. The current is 
   decreased by increasing the number of rows and decreasing the number
   of columns in the DRAM array. The number of columns defines the 
   "depth" of a page. A 2K device has a page depth of 2,048 -- whereas
   a 4K device has a page depth of 1,048. The DRAM controller in your 
   workstation/server determines the type of refresh it can support. 
   Some controllers only have 11 address drivers, so they are limited 
   to 2K refresh. Many newer DRAM controllers have been designed to 
   support both refresh standards. And still others support only 4K 
   refreshes.

   DRAM Adressing Effects
   +----------------------------+----------+----------+----------------+
   |          DRAM              |   Row    |  Column  |   Cell         | 
   +-----+------------+---------+ Adresses | Adresses | Retention (ms) |
   |Depth|Organization|Adressing|          |          |                |
   +-----+------------+---------+----------+----------+----------------+
   | 1Mb |  1M*4 or   | 10/10*  | A0 - A9  | A0 - A9  |       16       |
   |     |  1M*16     |         |          |          |                |
   +-----+------------+---------+----------+----------+----------------+
   | 2Mb |  2M*8      | 11/10   | A0 - A10 | A0 - A9  |       32       |
   |     |            |         |          |          |                |
   +-----+------------+---------+----------+----------+----------------+
   | 4Mb |  4M*1 or   | 11/11*  | A0 - A10 | A0 - A10 |    32 or 64    |
   |     |  4M*4      | or 12/10| A0 - A11 | A0 - A9  |                |
   +-----+------------+---------+----------+----------+----------------+
   * Also referred to as symetrical or square addressing.

   Memory refresh problems will occur if all of the required row columns
   are not refreshed. The memory system designer is advised to ensure 
   the memory refresh generation portion of the memory controller logic
   correctly accommodates the requirements of all the SIMMs to be supp-
   orted.
 
   How Do I Know I'm Buying the Correct Memory?
   Purchase memory from a reputable vendor that has the knowledge, 
   experience, and support to design and manufacture memory upgrades
   that are targeted for your particular system.


   Das DRAM Glossar

     Kapitel What's the Difference Between 1K, 2K and 4K Refresh?, Seite 1