Topic : Chips 'n Chips
Author : Michael Ruge
Version : chips_x.hyp (01/05/2001)
Subject : Dokumentation/Hardware
Nodes : 1505
Index Size : 35662
HCP-Version : 3
Compiled on : Atari
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INTRODUCTION
To meet the demand for a low cost compact LSI Floppy Disk Control-
ler device, Western Digital has developed the WD1772-02. The
WD1772-02 is an NMOS Floppy Disk Controller device that incorpora-
tes the FD179X, a digital data separator und write precompensation
circuitry all in a single chip. The device offers soft sectors for-
matting, selectable stepping rates, automatic track seek with ve-
rify, and variable sector lengts. The WD1772-02 comes in a 28-pin
dual-in-line or quad pack und operates from a single 5 Volt only
power supply.
APPLICATIONS
The Mini-Floppy Controller is targeted for the low cost sector of
the disk drive market, where digital data separation is preferred
over analog . Included in this market are Personal
Computers, Portable Computers und Small Business Computers.
HOST INTERFACING
Interfacing to a Host processor is accomplished through the eight
bit bi-directional Data Access Lines (DAL) und associated control
lines. The DAL is used to transfer data, status, and control words
out of or into WD1772-02. The DAL having three states enabled as an
output when Chip Select (CS) is active low and Read/Write (R/W) is
high or as input receiver when CS und R/W is low. When transfer of
data with the device is required by the Host CS is made low. The
address bits A0 and A1 combined with the R/W line select the regi-
ster und the direction of data.
During Direct Memory Acces (DMA) data transfers between the
WD1772-02 und Host Memory, the Data Request (DRQ) line is used in
Data Transfer Control. This signal also appears as status bit 1 du-
ring Read/Write operations. On Disk Read operations the DRQ is ac-
tive when an assembled byte is present in the Data Register, then
reset when read by the Host. If the Host fails to read the Data Re-
gister before the following byte is assembled in the Data Register,
the lost data bit is set in Status Register.
At the completion of every command INTRQ is asserted. INTRQ is de-
asserted by either reading the status or by loading the command
Register.
DISKETTE DRIVE INTERFACING
The WD1772-02 has two modes of operation depending on the state of
DDEN, regardless of the state DDEN the CLK input remains at 8Mhz.
Disk Reads with sector lengths of 128, 256, 512 und 1024 byte sec-
tor in both FM or MFM from diskettes is accomplished via the inter-
nal digital data separator. Disk Write operation in MFM on inner
tracks may require write precompensation. Write precompensation is
enabled when bit 1 = 0, in the Write command and a precompensation
value of 187 nsec is produced. The diskettes spindle motor is con-
trolled by bit 3 of any Type I, II oder III command, upon receiving
a command with bit 3 = 0, the spin up sequence is enabled.
weiterblättern
Kapitel Ein Kurzauszug aus der Dokumentation zum WD1772, Seite 1