Topic       : Documentation of the CT60
Author      : Didier MEQUIGNON
Version     : Version 2.00 (December 11, 2010)
Subject     : Documentation
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View Ref-File10.8  060 BURST with SDRAM                                        CT60

The CT60 bus clock = the 060 clock (060 in 'Full Bus mode').

The 060 uses  LINE BURST  to & from the system memory. SDRAM is well
adapted for a such processor !

A BURST LINE is a length of  4 LONG-WORDs (16 Bytes)  that are
transferred with only :

 PAGE HIT  (access to a logical SDRAM page already open) :

   ∙ 3,1,1,1 = 6 cycles for Burst Writes. Rate is 16 Bytes / 6 cycles
     = 178 MBytes/s (Each access in the same page).

   ∙ 5,1,1,1 = 8 cycles for Burst Reads. Rate is 16 Bytes / 8 cycles
     = 132 MBytes/s (Each access in the same page).

 PAGE MISS  (access to a new logical SDRAM page (must be precharged
and open) :

   ∙ 7,1,1,1 = 10 cycles for Burst Writes. Rate is 16 Bytes / 10
     cycles = 107 MBytes/s (Each access in a new page).

   ∙ 9,1,1,1 = 12 cycles for Burst Reads. Rate is 16 Bytes / 12
     cycles = 89 MBytes/s (Each access in a new page).

The CT60 uses the 060 at the top of the possible performances with
the mighty  COPYBACK  mode ! Instead of the WRITETROUGH mode like
other TOS machines !

 Copyback mode is active for all SDRAM memory area. 

Copyback mode allows the 060 to write into the cache without writting
into the SDRAM, what is so more performant ! The cache lines are
pushed into SDRAM only when needed (060 needs place by example). With
 two 8Kbytes caches,  it gives to coders the possibility to do some
incredibly speed routs residing at 100% into the caches !

The 060 uses BURST transfers with SDRAM in 99% of the cases. Here are
the cases when the 060 don't burst, this means, transfers Bytes,
Words & Long-Words :

 Byte, Word, and Long-Word READ Transfer Cycles from SDRAM 

Accesses that are implicitly NONCACHABLE :

   ∙ Locked Read-Modify-Write accesses.

   ∙ Table Searches.

Accesses that are not allocate in the data cache on a read miss :

   ∙ Exception Vector Fetches.

   ∙ Exception stack Deallocation for an RTE Instruction.

 Byte, Word, and Long-Word WRITE Transfer Cycles to SDRAM 

Accesses that are implicitly NONCACHABLE :

   ∙ Locked Read-Modify-Write accesses.

   ∙ Table Searches.

Accesses that are not allocate in the data cache on a write miss :

   ∙ Exception stacking.

Cache Line pushes for lines containing a single dirty Long-word.

Write to WRITETHROUGH pages (ST-RAM !).

 Remark : 

For those of you who are a bit familiar with 64-bit processors like
PPC, don't forget that the syntax for data size is not the same :

 With 32-Bit processors : 

   ∙ A WORD designates a 16-Bit entity.

   ∙ LONG-WORD designates a 32-Bit entity.

 With 64-Bit processors : 

   ∙ A HALF-WORD designates a 16-Bit entity.

   ∙ A WORD designates a 32-Bit entity.

   ∙ A DOUBLE-WORD designates a 64-Bit entity.