Topic : MC56001 Documentation Author : JAY Software Version : 1.0 (19/11/1997) Subject : Programming/Assembler Nodes : 152 Index Size : 4106 HCP-Version : 4 Compiled on : Atari @charset : atarist @lang : @default : @help : @options : -i +y +z -t4 @width : 100 View Ref-FileDIV Divide Iteration Operation: If D[55] ^ S[23] = 1 55 47 23 0 +----+------------+------------+ then |<---|<-----------|<-----------| <- C + S -> D +----+------------+------------+ Destination Accumulator D 55 47 23 0 +----+------------+------------+ else |<---|<-----------|<-----------| <- C - S -> D +----+------------+------------+ Destination Accumulator D where ^ denotes the logical exclusive OR operator Assembler Syntax: DIV S,D Description: Divide the destination operand D by the source operand S and store the result in the destination accumulator D. The 48-bit dividend must be a positive fraction which has been sign extended to 56-bits and is stored in the full 56-bit destination accumulator D. The 24-bit divisor is a signed fraction and is stored in the source operand S. Each DIV iteration calculates one quotient bit using a nonrestoring fractional division algorithm (see description). After the execution of the first DIV instruction, the destination operand holds both the partial remainder and the formed quotient. The partial remainder occupies the high-order portion of the destination accumulator D and is a signed fraction. The formed quotient occupies the low-oreder portion of the destinatioin accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient is shifted into the LS bit of the destination accumulator at the start of each DIV iteration. The formed quotientis the true quotient if the true quotient is positive. If the true quotient is negative, the formed quotient must be negated. Valid result are obtained only when |D| < |S| and the operands are interpreted as fractions. Note that this condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and precludes division by zero. The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder. To produce an N-bit quotient, the DIV instruction is executed N times where N is the number of bits of precision desired in the quotient, 1 <= N <= 24. Thus, for a full-precision (24-bit) quotient, 24 DIV iterations are required. In general, executing the DIV instruction N times produces an N-bit quotient and a 48-bit remainder which has (48-N) bits of precision and whose N MS bits are zeros. The partial remainder is not a true remainder and must be corrected due to the nonrestoring nature of the division algorithm before it may be used. Therefore, once the divide is complete, it is necessary to reverse the last DIV operation and restore the remainder to obtain the true remainder. The DIV instruction uses a nonrestoring fractional division algorithm which consists of the following operations (see the previous Operation diagram): 1. Compare the source and destination operand sign bits: An exclusive OR operation is performed on bit 55 of the destination operand D and bit 23 of the source operand S; 2. Shift the partial remainder and the quotient: The 55-bit destination accumulator D is shifted one bit to the left. The carry bit C is moved into the LS bit (bit 0) of the accumulator; 3. Calculate the next quotient bit and the new partial remainder: The 24-bit source operand S (signed divisor) is either added to or subtracted from the MSP portion of the destination accumulator (A1 or B1), and the result is stored back into the MSP portion of that destination accumulator. If the result of the exclusive OR operation was a '1' (i.e., the sign bits were different), the source operand S is added to the accumulator. If the result of the exclusive OR operation was a '0' (i.e., the sign bits were the same), the source operand S is subtracted from the accumulator. Due to the automatic sign extension of the 24-bit sign extension of the 24-bit signed divisor, the addition or subtraction operation correctly sets the carry bit C of the condition code register with the next quotient bit. Example: (4-Quadrant division, 24-bit signed quotient, 48-bit signed remainder) ABS A A,B ;make dividend positive, copy A1 to B1 EOR X0,B B,X:$0 ;save rem. sign in X:$0, quo. sign in N AND #$FE,CCR ;clear carry bit C (quotient sign bit) REP #$18 ;form a 24-bit quotient DIV X0,A ;form quotient in A0, remainder in A1 TFR A,B ;save quotient and remainder in B1,B0 JPL SAVEQUO ;go to SAVEQUO if quotient is positive NEG B ;complement quotient if N bit set SAVEQUO: TFR X0,B B0,X1 ;save quo. in X1, get signed divisor ABS B ;get absolute value of signed divisor ADD A,B ;restore remainder in B1 JCLR #23,X:$0,DONE ;go to DONE if remainder is positive MOVE #$0,B0 ;clear LS 24 bits of B NEG B ;complement remainder if negative DONE: Before Execution: A = $00:0E66D7:F2832C X0 = $123456 X1 = $000000 B = $00:000000:000000 After Execution: A = $FF:EDCCAA:654321 X0 = $123456 X1 = $654321 B = $00:000100:654321 Explanation of Example: Prior to execution, 56-bit A accumulator contains the 56-bit, signed-extended fractional dividend D (D=$00:0E66D7:F2832C = 0.112513535894635 approx.) and the 24-bit X0 register contains the 24-bit, signed fractional divisor S (S = $123456 = 0.142222166061401). Since |D|<|S|, the execution of the previous divide routine stores the correct 24-bit signed quotient in the 24-bit X1 register (A/X0 = 0.79111111164093 = $654321 = X1). The partial remainder is restored by reversing the last DIV operation and adding back the absolute value of the signed divisor i X0 remained in the 24-bit B1 register. Note that the remainder is really a 48-bit value which has 24 bits of precision. Thus, the correct 48-bit remainder is $000000:000100 which equals 0.0000000000018190 approximately. Note that the divide routine used in the previous example assumes that the sign-extended 56-bit signed fractional dividend is stored in the A accumulator and that the 24-bit signed fractional dividend is stored in the X0 register. This routine produces a ful 24-bit signed quotinet and a 48-bit signed remainder. This routine may be greatly simplified for the case in which only positive, fractional operands are used to produce a 24-bit positive quotient and a 48-bit positive remainder, as shown in the following example: 1-Quadrant division, 24-bit unsigned quotient, 48-bit unsigned remainder AND #$FE,CCR ;clear carry bit C (quotient sign bit) REP #$18 ;form a 24-bit quotint and remainder DIV X0,A ;form quotient in A0, remainder in A1 ADD X0,A ;restore remainder in A1 Note that this routine assumes that the 56-bit positive, fractional, sign-extended dividend is stored in the A accumulator and that the 24-bit positive, fractional divisor is stored in the X0 register. After execution, the 24-bit positive fractional quotient is stored in the A0 register; the LS 24 bits of the 48-bit positive fractional remainder are stored in the A1 register. There are many variations possible when choosing a suitable division routine for a given application. The selection of a suitable division routine normally involves specification of the following items: 1) the number of bits precision in the dividend; 2) the number of bits of precision N in quotient; 3) whether the value of N is fixed or is variable; 4) whether the operands are unsigned or signed; 5) whether or not the remainder is to be calculated. For extended precision division (i.e., for N-bit quotients where N>24), the DIV instruction is no longer applicable, and a user-defined N-bit division routine is required. Condition codes: 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |<- MR ->|<- CCR ->| L- Set if overflow bit V is set V- Set if the MS bit of the destination operand is changed as a result of the instruction's left shift operation C- Set if bit 55 of the result is cleared Instruction Format: DIV S,D S = (X0,Y0,X1,Y1) D = (A,B) Timing: 2 oscillator clock cycles Memory: 1 program word