Topic       : Documentation of the CT60
Author      : Didier MEQUIGNON
Version     : Version 2.00 (December 11, 2010)
Subject     : Documentation
Nodes       : 135
Index Size  : 3664
HCP-Version : 3
Compiled on : Atari
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View Ref-File10.6.1  EEPROM DATA                                               CT60

The DIMM standard allows the loading of the manufacturer informations
from a small 128 or 256 bytes EEPROM on the DIMM. Some of these
informations are needed to configure the SDRAM controller of the
CT60.

The following bytes are uses by the CT60 :

   ∙  Bold  are used by the boot software to configure the SDRAM
     controller.

   ∙ Others are used only as user information in a SET UP menu.


 Byte 2      Memory Type                 FPM, EDO, NIBBLE, SDRAM (=$04) 
  
 Byte 3      Number of Row Addresses     11,12,13,. : $B:11 / $C:12 / $D:13
 Byte 4      Number of Column Addresses  8,9,10,... : $8:8  / $9:9  / $A:10
 Byte 5      Number of DIMM Banks        1 or 2  $01:1 / $02:2 
  
 Byte 6-7    Module Data Width           64, 72 , 80, : $4000 
 Byte 8      Voltage Interface Level     TTL, LVTTL (1), HSTL, SSTL3, SSTL2
             of this assembly 
 Byte 9      SDRAM Cycle Time (tCYC) 
 Byte 10     SDRAM Access from Clock 
             (tAC) 
 Byte 11     SDRAM Configuration Type    None, Parity, ECC 
  
 Byte 12     Refresh Rate                15.625uS:$80, 7.81uS:$82 
  
 Byte 17     Number of Banks             2 or 4 ($04) 
             on SDRAM Device 
 Byte 27     Minimum ROW Precharge 
             Time (tRP) 
 Byte 28     Minimum ROW Active to 
             Active Delay (tRRD) 
 Byte 29     Minimum RAS to CAS Delay 
             (tRCD) 
  
 Byte 31     Module Bank Density         16 ($04), 32 ($08), 64 ($10), 
                                         128 ($20), 256 ($40), 512 ($80) 
  
 Byte 64-71  Module Manufacturers        EX : $A4000000 = IBM 
             JEDEC ID Code 
 Byte 73-90  Module Part Number 
 Byte 93-94  Module Manufacturing Date 
 Byte 95-98  Module Serial Number 


Some features are initialized by the logic chip into the DIMM module
when booting :

   ∙ BURST Length 1, 2, 4, 8 , Page. 4 is for 060, PPC, X86
     processors

   ∙ CAS Latency 2, 3, 4,... 2 is possible with PC100 at 66 up to 80
     MHz !

 Remarks : 

   ∙ Don't confuse SDRAM banks (2 or 4) with DIMM banks (1 or 2) !

   ∙ Bytes 128-255 are open for Customer Use and can be written - Not
     used with CT60.

   ∙ DIMM Density = Module Bank Density * Number of DIMM Banks (1 or
     2).