Topic       : Documentation of the CT60
Author      : Didier MEQUIGNON
Version     : Version 2.00 (December 11, 2010)
Subject     : Documentation
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Index Size  : 3664
HCP-Version : 3
Compiled on : Atari
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View Ref-File10.4  HARDWARE EMULATION                                          CT60

The CT60 allows a  Falcon hardware emulation. 

With this Hardware Emulation Window, it is easy to implement a new
chip replacing the old one of the Falcon motherboard and this at the
same address(es) !

 Examples : 

   ∙ SUPER-VIDEL chip in a FPGA with DDR memory.

   ∙ SDRAM replacement of a part of the ST-RAM at the same addresses.

   ∙ ACIA for new PS/2 ports with a CPLD/FPGA.

   ∙ ACIA MIDI with a CPLD/FPGA.

   ∙ DSP56301 replacing 56001 at same addresses !

   ∙ FPGA emulating serial & parallel port of the Falcon (Zilog 85C30
     and Yamaha).

   ∙ New SDMA for Audio.

There is a time window from the start of the 060 access to the Falcon
addresses ($00xxxxxx and $FFxxxxxx) up to the start (rising edge) of
the 7th cycle of the CLK (bus and 060 clock).

When the 060 inserts the addresses and TS to validate, a counter into
ABE start if the address is somewhere in the Falcon address space.
Until the counter reaches the end of the 6th cycle, a card on the 060
slot bus of the CT60 can answer to terminate the access instead of a
chip of the Falcon mb (with TA/ or TEA/ or both TA/ & TEA/ for a
RETRY). This termination of the access terminates the counter and
invalidates the Falcon acccess that was started.

At the begining of the 7th cycle the Falcon READ access continues and
cannot be stopped. ABE drives data on the CT60 bus.

The time limit for the termination signal sampling is the end of the
6th cycle.

 If you want to use SDRAM on a daughter card : 

For 66 MHz SDRAM BURST READ you need 5-1-1-1 cycles. The TA arrives
the 5th cycle (first data) up to 8th (fourth data). This TA arrives
before the end of the 6th cycle and the F030 access start is
cancelled.

For 66 MHz SDRM BURST WRITE you need 3-1-1-1 cyles. The TA arrives
the 3rd cycle (first data) up to 6th (fourth data). This TA arrives
before the end of the 6th cycle and the F030 access start is
cancelled.

 For registers accesses on a daughter card, you need 2 or 3 cycles. 

If you want to write both to F030 mb AND your daughter card (an
address that is present on the two boards), don't send TA from the
daughter card and the TA from mb will terminate the write access for
you.

 By example,  this technic allows to write all VIDEL and SUPER VIDEL
registers in the same time. The emulation is total! The only thing is
to do is to implement a bit in the daughter board to  switch ON/OFF
the emulation. 

 If the switch is ON : 

   ∙ the daugther card address registers are at the same addresses
     than the F030 mb and :

   ∙ the TA must not be sent when writting these registers that are
     common to F030 and the daughter card.

   ∙ the TA must be sent before the 7th cycle when reading from
     register that is a common to F030 & daughter card.

 If the switch is OFF : 

   ∙ the daughter card address registers must be present at some
     specific addresses (not the same than the F030) and the TA is
     sent as usual by the daughter card for all read & write
     accesses.

 Example with $FFFF820E : 

Switch is ON -> Write at $FFFF820E write to daughter card and F030 mb
and this access is terminated by the TA from Falcon mb (ABE). The
card don't send TA.

Switch is OFF -> Write at $FFFF820E write only to Falcon mb. You need
to write to a 'new' address on the card to access the same register.