Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
@width      : 100
View Ref-FileBSET                        Bit Test and Set

Operation:
    D[n] -> C;
    1 -> D[n]

Assembler Syntax:
    BSET    #n,X:ea
    BSET    #n,X:aa
    BSET    #n,X:pp
    BSET    #n,Y:ea
    BSET    #n,Y:aa
    BSET    #n,Y:pp
    BSET    #n,D

Description:
    Test the nth bit of the destination operand D, set it, and store
the result in the destination location. The state of the nth bit is
stored in the carry bit C of the condition code register. After the
test, the nth bit of the destination location is set. The bit to be
tested is selected by an immediate bit number from 0-23. This
instruction performs a read-modify-write operation on the destination
location using two destination accesses before releasing the bus. This
instruction provides a test-and-set capability which is useful for
synchronizing multiple processorsusing a shared memory. This
instruction can use all memory alterable addressing modes.

Example:
    BSET    #$0,X:<<$FFE5   ;test and set bit 10 in I/O Port C Data Reg.

    Before Execution:
        X:$FFE5 = $000000
        SR      = $0300

    After Execution:
        X:$FFE5 = $000001
        SR      = $0300

Explanation of Example:
    Prior to execution, the 24-bit X memory location X:$FFE5 (I/O port
C data register) contains the value $000000. The execution of the BSET
#$0,X:<<$FFE5 instruction test the state of the 0th bit in X:$FFE5,
sets the carry bit C accordingly, and then sets the 0th bit in X:$FFE5.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

CCR Condition Codes:
    For destination operand SR:
        C- Changed if bit 0 is specified. Not affected otherwise.
        V- Changed if bit 1 is specified. Not affected otherwise.
        Z- Changed if bit 2 is specified. Not affected otherwise.
        N- Changed if bit 3 is specified. Not affected otherwise.
        U- Changed if bit 4 is specified. Not affected otherwise.
        E- Changed if bit 5 is specified. Not affected otherwise.
        L- Changed if bit 6 is specified. Not affected otherwise.

    For other destination operands:
        C- Set if bit tested is set. Cleared otherwise.
        V- Not Affected.
        Z- Not Affected.
        N- Not Affected.
        U- Not Affected.
        E- Not Affected.
        L- Not Affected.

MR Status Bits:
    For destination operand SR:
        I0- Changed if bit 8 specified. Not affected otherwise.
        I1- Changed if bit 9 specified. Not affected otherwise.
        S0- Changed if bit 10 specified. Not affected otherwise.
        S1- Changed if bit 11 specified. Not affected otherwise.
        T - Changed if bit 13 specified. Not affected otherwise.
        LF- Changed if bit 15 specified. Not affected otherwise.

    For other destination operands:
        I0- Not affected
        I1- Not affected
        S0- Not affected
        S1- Not affected
        T - Not affected
        LF- Not affected

Instruction Format:
    BSET    #n,X:ea
    BSET    #n,Y:ea
    BSET    #n,X:aa
    BSET    #n,Y:aa
    BSET    #n,X:pp
    BSET    #n,Y:pp
    BSET    #n,D

    #n = bit number

    ea = (Rn)-Nn
         (Rn)+Nn
         (Rn)-
         (Rn)+
         (Rn)
         (Rn+Nn)
         -(Rn)
         Absolute address

    aa = 6-bit Absolute Short Address

    pp = 6-bit I/O Short Address

    D  = (  X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,
            Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC)

Timing:     4 + mvb oscillator clock cycles

Memory:     1 + ea program words