Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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View Ref-FileAND                     Logical AND

Operation:
    S & D[47:24] -> D[47:24] (parallel move)
    where & denotes the logical AND operator

Assembler Syntax:
    AND S,D             (parallel move)

Description:
    Logically AND the source operand S with bits 47-24 of the
destination operand D and store the result in bits 47-24 of the
destination accumulator. This instruction is a 24-bit operation. The
remaining bits of the destination operand D are not affected.

Example:
    AND X0,A    (R5)-N5     ;AND X0 with A1, update R5 using N5

    Before Execution:
        X0 = $FF0000
        A  = $00:123456:789ABC

    After Execution:
        X0 = $FF0000
        A  = $00:120000:789ABC

Explanation of Example:
    Prior to execution, the 24-bit X0 register contains the value
$FF0000, and the 56-bit A accumulator contains the value
$00:123456:789ABC. The AND X0,A instruction logically ANDs the 24-bit
value in the X0 register with bits 47-24 of the A accumulator (A1)
and stores the result in the the A accumulator with bits 55-48 and
23-0 unchanged.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting has occured during parallel move
    N- Set if bit 47 of A or B result is set
    Z- Set if bits 47-24 A or B result are zero
    V- Always cleared

Instruction Format:
    AND S,D

    S = (X0,X1,Y0,Y1)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words