Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
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View Ref-FileADDR                        Shift Right and Add Accumulators

Operation:
    S + D / 2 -> D      (parallel move)

Assembler Syntax:
    ADDR    S,D         (parallel move)

Description:
    Add the source operand S to one-half the destination operand D and
store the result in the destination accumulator. The destination operand
D is arithmetically shifted one bit to the right while the MS bit of D
is held constant prior to the addition operation. In contrast to the
ADDL instruction, the carry bit is always set correctly, and the
overflow bit can only be set by the addition operation and not by an
overflow due to the initial shifting operation. This instuction is
useful for efficient divide and decimation in time (DIT) FFT
algorithms.

Example:
    ADDR    B,A X0,X:(R1)+N1 Y0,Y:(R4)-     ;B+A/2 -> A, save X0 and Y0

    Before execution:
        A = $80:000000:2468AC
        B = $00:013570:000000
    After execution:
        A = $C0:013570:123456
        B = $00:013570:000000

Explanation of Example:
    Prior to execution, the 56-bit A accumulator contains the value
$80:000000:2468AC, and the 56-bit B accumulator contains the value
$00:013570:000000. The ADDR B,A instruction adds one-half the value
in the A accumulator to the value in the B accumulator and stores
the 56-bit result in the A accumulator.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if limiting (parallel move) or overflow has occured in result
    E- Set if the signed integer portion of A or B result is in use
    U- Set if A or B result is unnormalized
    N- Set if bit 55 of A or B result is set
    Z- Set if A or B result equals zero
    V- Set if overflow has occured in A or B result
    C- Set if a carry (or borrow) occurs from bit 55 of A or B result

NOTE: The definition of the E and U bits varies according to the
scaling mode being used.

Instruction Format:
    ADDR    S,D

    S = (A,B)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words