Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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@options    : -i +y +z -t4
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View Ref-FileADDL                        Shift Left and Add Accumulators

Operation:
    S+2*D -> D          (parallel move)

Assembler Syntax:
    ADDL    S,D         (parallel move)

Description:
    Add the source operand S to two times the destination operand D and
store the result in the destination accumulator. The destination
operand D is arithmecally shifted one bit to the left, and a zero is
shifted into the LS bit of D prior to the addition operation. The carry
bit is set correctly if the source operand does not overflow as a
result of the left shifte operation. The overflow bit may be set as a
result of either the shifting or addition operation (or both). This
instruction is useful for efficient divide and decimation int time
(DIT) FFT algorithms.

Example:
    ADDL    A,B #$0,R0      ;A + 2 * B -> B, set up addr. reg. R0

    Before Execution:
        A = $00:000000:000123
        B = $00:005000:000000

    After Execution:
        A = $00:000000:000123
        B = $00:00A000:000123

Explanation of example:
    Prior to execution, the 56-bit accumulator contains the value
$00:000000:000123, and the 56-bit B accumulator contains the value
$00:005000:000000. The ADDL A,B instruction adds two times the value
in the B accumulator to the value in the A accumulator and stores the
56-bit result in the B accumulator.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if limiting (parallel move) or overflow has occured in result
    E- Set if the signed integer portion of A or B result is in use
    U- Set if A or B result is unnormalized
    N- Set if bit 55 of A or B result is set
    Z- Set if A or B result equals zero
    V- Set if overflow has occured in A or B result or if the MS bit of
       the destination operand is changed as a result of the instruction's
       left shift
    C- Set if a carry (or borrow) occurs from bit 55 of A or B result

NOTE: The definition of the E and U bits varies according to the
scaling mode being used.

Instruction Format:
    ADDL    S,D

    S = (A,B)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words