Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
@width      : 100
View Ref-FileADD                     Add

Operation:
    S+D -> D            (parallel move)

Assembler Syntax:
    ADD S,D             (parallel move)

Description:
    Add the source operand S to the destination operand D and store the
result in the destination accumulator. Words (24 bits), long words (48
bits), and accumulators (56 bits) may be added to the destination
accumulator.

NOTE: The carry bit is set correctly using word and long-word source
operands if the extension register of the destination accumulator (A2
or B2) is the sign extension of bit 47 of the destination accumulator
(A or B). Thus, the carry bit is always set correctly using accumulator
source operands, but can be set incorrectly if A1, B1, A10, or B10 are
used as source operands and A2 and B2 are not replicas of bit 47.

Example:
    ADD X0,A A,X1   A,Y:(R1)+   ;24-bit add,set up X1, save prev, result
 
    Before Execution:
        X0 = $FFFFFF
        A  = $00:000100:000000

    After Execution:
        X0 = $FFFFFF
        A  = $00:0000FF:000000

Explanation of Example:
    Prior to execution, the 24-bit X0 register contains the value
$FFFFFF and the 56-bit A accumulator contains the value
$00:000100:000000. The ADD instruction automatically appends the 24-bit
value in the X0 register with 24 LS zeros, sign extends the resulting
48-bit long word to 56 bits, and adds the result to the 56-bit A
accumulator. Thus, 24-bit operands are are added to the MSP portion of
A or B (A1 or B1) because all arithmetic instructions assume a
fractional, twos complement data representation. Note that 24-bit
operands can be added to the LSP portion of A or B (A0 or B0) by loading
the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or
Y1 with the sign extension of X0 or Y0 and executing an ADD X,A or
ADD Y,A instruction.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if limiting (parallel move) or overflow has occured in result
    E- Set if the signed integer portion of A or B result is in use
    U- Set if A or B result is unnormalized
    N- Set if bit 55 of A or B result is set
    Z- Set if A or B result equals zero
    V- Set if overflow has occured in A or B result
    C- Set if a carry (or borrow) occurs from bit 55 of A or B result

NOTE: The definition of the E and U bits varies according to the
scaling mode being used.

Instruction Format:
    ADD S,D

    S = (A,B,X,Y,X0,Y0,X1,Y1)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words