Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
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View Ref-FileADC                     Add Long with Carry

Operation:
    S+C+D -> D          (parallel move)

Assembler Syntax:
    ADC S,D             (parallel move)

Description:
    Add the source operand S and the carry bit C of the condition code
register to the destination operand D and store the result in the
destination accumulator. Long words (48 bits) may be added to the
(56-bit) destination accumulator.

NOTE: The carry bit is set correctly for multiple precision arithmetic
using long word operands if the extension register of the destination
accumulator (A2 or B2) is the sign extension of bit 47 of the
destination accumulator (A or B).

Example:
    MOVE    L:<$0,X         ;get a 48-bit LS long-word operand in X
    MOVE    L:<$1,A         ;get other LS long word in A (Sing ext.)
    MOVE    L:<$2,Y         ;get a 48-bit MS long-word operand in Y
    ADD     X,A L:<$3,B     ;add LS words; get other MS word in B
    ADC     Y,B A10,L:<$4   ;add MS words with carry, save LS sum
    MOVE    B10,L:<$5       ;save MS sum

    Before Execution:
        A = $FF:800000:000000
        X = $800000:000000
        B = $00:000000:000001
        Y = $000000:000001
 
    After Execution:
        A = $FF:000000:000000
        X = $800000:000000
        B = $00:000000:000000
        Y = $000000:000001

Explanation of Example:
    This example illustrates long-word double-precision (96-bit) addition
using the ADC instruction. Prior to execution of the ADD and ADC
instructions, the double-precision 96-bit value
$000000:000001:800000:000000 is loaded into the Y and X registers (Y:X),
respectively. The other double-precision 96-bit value
$000000:000001:800000:000000 is loaded into the B and A accumulators
(B:A), respectively. Since the 48-bit value loaded into the A
accumulator is automatically sign extended to 56 bits and the other
48-bit long-word operand is internally sign extended to 56 bits during
instruction execution, the carry bit wil be set correctly after the
execution of the ADD X,A instruction. The ADC Y,B instruction then
produces the correct MS 56-bit result. The actual 96-bit result is
stored in memory using the A10 and B10 operands (instead of A and B)
because shifting and limiting is not desired.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if limiting (parallel move) or overflow has occured in result
    E- Set if the signed integer portion of A or B result is in use
    U- Set if A or B result is unnormalized
    N- Set if bit 55 of A or B result is set
    Z- Set if A or B result equals zero
    V- Set if overflow has occured in A or B result
    C- Set if a carry (or borrow) occurs from bit 55 of A or B result

NOTE: The definition of the E and U bits varies according to the
scaling mode being used.

Instruction Format:
    ADC S,D

    S = (X,Y)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words