Topic : TOS - das Betriebssystem Author : Version : tos.hyp (5. März 2013) Subject : Programmieren/Atari Nodes : 3001 Index Size : 93602 HCP-Version : 5 Compiled on : Atari @charset : atarist @lang : @default : Titel @help : @options : +g -i -s +x +zz -t4 @width : 70 View Ref-File4.21.16 PCI_RSC_DESC TOS typedef struct { uint16_t next; /* Länge dieser Struktur in Bytes, dient zur */ /* Ermittlung des nächsten Deskiptors */ uint16_t flags; /* Resourcen-Typ und verschiedene andere Flags */ uint32_t start; /* Startadresse der Resource im PCI Adreßbereich, */ /* ist die Resource nicht direkt ansprechbar, */ /* so ist die Adresse 0 */ uint32_t length; /* Länge der Resource */ uint32_t offset; /* Offset von der physikalischen CPU-Adresse */ /* zur PCI-Adresse */ uint32_t dmaoffset; /* Offset für DMA-Transfers vom/zum Hauptspeicher */ } PCI_RSC_DESC; Um den Deskriptor der nächsten Resource des PCI-Gerätes zu ermitteln, muß man zur Startadresse des aktuellen Deskriptors das Feld next addieren. Das Feld start gibt den Beginn der entsprechenden Resource im PCI-Adreßbereich an. Falls diese Resource nicht direkt ansprechbar sein sollte, so steht in diesem Feld die Adresse 0. Über length kann man schließlich die Länge dieser Resource bestimmen. Der PCI- Adreßbereich ist im allgemeinen nicht mit der von der CPU aus gesehenen Adresse gleichzusetzen. Der Adreß-Offset, der zur PCI- Adresse zu addieren ist, um die physikalische Adresse für die CPU zu ermitteln, ist im Feld offset abgelegt.Der Eintrag dmaoffset gibt schließlich den Offset an, der zur PCI-Adresse addiert werden muß, wenn es sich um DMA-Transfers handelt. Die Flags im Resource-Deskriptor RSC_ROM 0x2000 This is an expansion ROM (must be Memory, not IO) RSC_IO 0x4000 kennzeichnet einen I/O-Bereich, bei gelöschten Bit handelt es sich um einen memory-Bereich RSC_LAST 0x8000 letzte Resource für dieses PCI-Gerät FLG_8BIT 0x0100 8 Bit Zugriffe werden unterstützt FLG_16BIT 0x0200 16 Bit Zugriffe werden unterstützt FLG_32BIT 0x0400 32 Bit Zugriffe werden unterstützt FLG_ENDMASK 0x000F kennzeichnet das Byte Ordering: 0: Motorola (big endian) 1: Intel (little endian), address swapped 2: Intel (little endian), lane swapped 3..14: reserviert 15: unbekannt, Zugriff nur über BIOS möglich The start field contains the start address on the PCI bus of the resource. If the resource is not directly accessible, the start address is 0. The length field contains its length. The offset field contains the offset from physical CPU to PCI address for the resource - ie. the value that must be added to the PCI address to get the physical address in CPU address space. The dmaoffset gives the offset that a PCI bus master must add to a CPU memory address to access that address in main memory over the PCI BUS. What are all these byte orders? The PCI-bus is defined as a little endian byte ordering bus. The most significant byte of a multi-byte number is located at the lowest address occupied by this number. The 68xxx-series CPUs are big endian. PCI-bus and CPU are connected together by a host bridge which does some kind of format conversion. The PCI-BIOS knows about the format conversion performed by the host bridge. The PCI-BIOS does not know about any format conversion done (internally) by PCI devices. The driver has to know its device's properties and capabilities. The table shows what 68xxx data byte (top row) is connected to what PCI-bus data byte (lower right) by what 68xxx-access and format conversion (left column): 68xxx-CPU data bus bits D31..24 D23..16 D15..8 D7..0 ---------------------------------------------------- big endian 32-bit-access +0 D31..24 D23..16 D15..8 D7..0 16-bit-access +0 D15..8 D7..0 16-bit-access +2 D31..24 D23..16 8-bit-access +0 D7..0 8-bit-access +1 D15..8 8-bit-access +2 D23..16 8-bit-access +3 D31..24 ---------------------------------------------------- little endian, lane swapped 32-bit-access +0 D0..7 D15..8 D23..16 D31..24 16-bit-access +0 D0..7 D15..8 16-bit-access +2 D23..16 D31..24 8-bit-access +0 D0..7 8-bit-access +1 D15..8 8-bit-access +2 D23..16 8-bit-access +3 D31..24 ---------------------------------------------------- little endian, address swapped 32-bit-access +0 D31..24 D23..16 D15..8 D7..0 16-bit-access +0 D31..24 D23..16 16-bit-access +2 D15..8 D7..0 8-bit-access +0 D31..24 8-bit-access +1 D23..16 8-bit-access +2 D15..8 8-bit-access +3 D7..0 ∙ "Big endian" makes the PCI-bus appear as a big endian resource from the viewpoint of the 68xxx processor. It requires dynamic route changes in the host bridge and seems not to be implemented by any host bridge. ∙ "Little endian, lane swapped" is the easy way to make 8 bit per pixel modes work in the frame buffer of a PCI-device (VGA controller) which does not have its own format conversion. This mode is used in PCI-Macintoshs and for memory and IO accesses in the Milan. In this mode, the address needs no modifications. 8- bit accesses work normal, on 16 and 32 bit accesses endian conversion must be performed on the the read or written data (ror.w #8,d0 for 16 bit, ror.w #8,d0:swap d0:ror.w #8,d0 for 32 bit). ∙ "Little endian, address swapped" is the way to go if accesses to 32 bit registers or 32 bit per pixel frame buffers have top priority. In this mode, 32 bit accesses work without modifications. On 16 bit accesses, the address needs to be XOR'd with a value of 2, on 8-bit accesses the address is XOR'd with a value of 3. The data read or written is in correct format. Querverweis: get_resource