Topic       : Documentation of the CT60
Author      : Didier MEQUIGNON
Version     : Version 2.00 (December 11, 2010)
Subject     : Documentation
Nodes       : 135
Index Size  : 3664
HCP-Version : 3
Compiled on : Atari
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View Ref-File8.1  The 68060's caches                                           CT60

There are two caches of 8KB inside the 68060, data and instruction.

The ST-RAM is in writethrough, at each time than the 68060 write to
the RAM, he write in the same time than the data cache.

The SDRAM is in copyback, the 68060 write always inside his data
cache, he write in the memory the old data of his cache for found
some place for the new data.

The 68060 has also an instruction cache, witch the direct link with
the data cache is only the memory. The result is than it's possible
to obtain incoherency between the data cache and the instruction
cache. The example is the exceution of a relocated program, without
precaution and without system call this is a crash.

The 68060 has the ability to watch or snoop the external bus during
accesses by other bus masters (like DMA or blitter), maintaining
coherency between the 68060's caches and external memory.