Topic       : Documentation of the CT60
Author      : Didier MEQUIGNON
Version     : Version 2.00 (December 11, 2010)
Subject     : Documentation
Nodes       : 135
Index Size  : 3664
HCP-Version : 3
Compiled on : Atari
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View Ref-File7.10  Informations about the SDRAM                                CT60

At this page you can see :

   ∙ The Memory Type (SDRAM).

   ∙ The Number of Row Addresses.

   ∙ The Number of Column Addresses.

   ∙ The Number of DIMM Banks (1 or 2).

   ∙ The Module Data Width (64).

   ∙ The Voltage Interface Level (LVTTL).

   ∙ The SDRAM Cycle Time (for example 10 nS if PC100).

   ∙ The SDRAM Access from Clock.

   ∙ The SDRAM Configuration Type (no parity).

   ∙ The SDRAM Refresh Rate (15.625 uS or 7.8 uS).

   ∙ The Number of Banks.

   ∙ The CAS Latency (2).

   ∙ The CS Latency (0).

   ∙ The WE Latency (0).

   ∙ The SDRAM Module Attributes (unbuffered).

   ∙ The Minimum Row Precharge Time.

   ∙ The Minimum Row Active to Active Delay.

   ∙ The Minimum RAS to CAS Delay.

   ∙ The Minimum RAS Pulse Width.

   ∙ The Module Bank Density (in MB).

   ∙ The Module Manufacturers ID (in hexa/ASCII).

   ∙ The Module Part Number (in ASCII).

   ∙ The Module Manufacturing Date (week/year).

This values are stored inside a little EEPROM on the module.