Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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@options    : -i +y +z -t4
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View Ref-FileSSI Transmit Interrupt Enable (TIE) CRB Bit 14:

   The DSP will be interrupted when TIE and the TDE flag in the SSI
status register is set. When TIE is cleared, this interrupt is disabled.
However, the TDE bit will always indicate the transmit data register empty
condition even when the transmitter is disabled with the TE bit. Writing
data to TX or TSR will clear TDE, thus clearing the interupt. Hardware and
software reset clear RE.

There are two transmit data interrupts that have separate interrupt vectors:

   1. Transmit data with exceptions -- This interrupt is generated on the
following condition:
    TIE=1, TDE=1, and TUE=1

   2. Transmit data without exceptions -- This interrupt is generated on the
following condition:
    TIE=1, TDE=1, and TUE=0