Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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View Ref-FileFrame Sync Length (FSL0,FSL1) CRB Bits 7,8:

    These bits select the type of frame sync to be generated or recognized.
If FSL1 equals zero and FSL0 equals zero, a word-length frame sync is
selected for both TX and RX that is the length of the data word defined by
bits WL1 and WL0. If FSL1 equals one and FSL0 equals zero, a 1-bit clock
period frame syncis selected for both TX and RX. When FSL0 equals one, the
TX and RX frame syncs are different lengths. Hardware reset and software
reset clear FSL0 and FSL1.

   +------+------+----------------------------------------------+
   | FSL1 | FSL0 |        Frame Sync Length                     |
   +------+------+----------------------------------------------+
   |  0   |  0   | WL bit clock for both TX/RX                  |
   +------+------+----------------------------------------------+
   |  0   |  1   | One-bit clock for TX and WL bit clock for RX |
   +------+------+----------------------------------------------+
   |  1   |  0   | One-bit clock for both TX/RX                 |
   +------+------+----------------------------------------------+
   |  1   |  1   | One-bit clock for RX and WL bit clock for TX |
   +------+------+----------------------------------------------+

Sync/Async (SYN) CRB Bit 9:

   SYN controls whether the receive and transmit functions of the SSI
occur synchronously with respect to each other. When SYN is cleared,
asynchronous mode is chosen and separate clock and frame sync signals are
used for the transmit and receive sections. When SYN is set, synchronous
mode is chosen and the transmit and receive sections use common clock and
frame sync signals. Hardware reset and software reset clear SYN.