Topic       : The ATARI Compendium
Author      : Scott Sanders / JAY Software
Version     : 1.25 (20/6/2003)
Subject     : Documentation
Nodes       : 1117
Index Size  : 32614
HCP-Version : 6
Compiled on : Atari
@charset    : UTF-8
@lang       : en
@default    : 
@help       : %About
@options    : +g -i -t4 +y +z
@width      : 100
View Ref-FileMC 68000
MC 68030
<invalid destination page 1581>

                             The 680x0 Processor


Atari computers use the Motorola MC68000 or MC68030. Third party devices
have also been created to allow the use of a MC68010, MC68020, or MC68040
processor. The system cookie '_CPU' should be used to determine the
currently installed processor. The following table lists the 680x0's
interrupt priority assignments:


Level  Assignment

  7    NMI

  6    MK68901 MFP

  5    SCC ∙On a computer without an SCC chip,
this interrupt is unused.


  4    VBLANK (Sync)

  3    VME Interrupter ∙∙On a computer without an VME bus,
this interrupt is unused.


  2    HBLANK (Sync)

  1    Unused

Interrupts may be disabled by setting the system interrupt mask (bits
8-10 of the SRStatus Register
 register) to a value higher than the interrupts you wish to
disable. Setting the mask to a value of 7 will effectively disable all
interrupts (except the level 7 non-maskable interrupt).

The Data/Instruction Caches

The Atari TT030 and Falcon030 contain onboard data and instruction
caches. These caches may be controlled by writing to the CACR register (in
supervisor mode). The following table lists longword values that may be
written to the CACR to enable or disable the caches:

Value to    Effect
Write to
  CACR

 0xA0A      Flush and disable both caches.

 0x101      Enable both caches.

 0xA00      Flush and disable the data cache.

 0x100      Enable the data cache.

   0xA      Flush and disable the instruction cache.

   0x1      Enable the instruction cache.