Topic : MC56001 Documentation Author : JAY Software Version : 1.0 (19/11/1997) Subject : Programming/Assembler Nodes : 152 Index Size : 4106 HCP-Version : 4 Compiled on : Atari @charset : atarist @lang : @default : @help : @options : -i +y +z -t4 @width : 100 View Ref-File A A A0 A1 A2 ABS ADC ADD ADDL ADDR Address Registers AND ANDI ASL ASR B B B0 B1 B2 BCHG BCLR BSET BTST C C Carry CCR Chip Mode Clock Source Direction CLR CM CMP CMPM Condition Code Register CRA CRB D Data ALU Accumulator Registers Data ALU Input Registers Data Rom Enable DC0 DC1 DC2 DC3 DC4 DE DIV DMA DMA Status DO E E EA ENDDO EOR Extension External Memory Access F Frame Rate Divider Control Frame Sync Length FSL0 FSL1 G Gated Clock Control GCK H HCIE HCP HCR HF0 HF1 HF2 HF3 HI Host Command Interrupt Enable Host Command Pending Host Control Register Host Flag 0 Host Flag 1 Host Flag 2 Host Flag 3 Host Interface Host Receive Data Full Host Receive Data Register Host Receive Interrupt Enable Host Status Register Host Transmit Data Empty Host Transmit Data Register Host Transmit Interrupt Enable HRDF HRIE HRX HSR HTDE HTIE HTX HYPertext Authors I I I I0 I1 IF0 IF1 ILLEGAL Instruction Set Interrupt 0 Interrupt 1 J Jan Krupka Jan Krupka Trnkova 26 Olomouc 779 00 Czech Republic tel.: +0420 068 5419108 E-mail: Krupkaj@risc.upol.cz fido. 2:421/36.15 WWW: http://www.inf.upol.cz/~krupkaj/ Jcc JCLR JMP JScc JSCLR JSET JSR JSSET L l L L: LA LC Limit loop Loop Address Register Loop Counter Register LSL LSR LUA M M0 M1 M2 M3 M4 M5 M6 M7 MA MAC MACR MB Mn MOD Mode Register Modifier Registers MOVE MOVEC MOVEM MOVEP MPY MPYR MR N N N0 N1 N2 N3 N4 N5 N6 N7 NEG Negative Nn NOP NORM NOT O OF0 OF1 Offset Registers OMR Operating Mode Register OR ORI Overflow P P0 P1 P2 P3 PC PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 Port B Prescale Modulus Select Prescaler Range Program Counter PSR R R R0 R1 R2 R3 R4 R5 R6 R7 R:Y RDF RE Receive Frame Sync Flag Receive Overrun Error Flag Registers REP RESET RFS RIE Rn RND ROE ROL ROR RTI RTS RX S S SBC SCD0 SCD1 SCD2 SCKD SD SE Serial Control 0 Direction Serial Control 1 Direction Serial Control 2 Direction Serial Input Flag 0 Serial Input Flag 1 Serial Output Flag 0 Serial Output Flag 1 SHFD Shift Direction SP SP Register Values SR SS SSH SSI SSI Control Register A SSI Control Register B SSI Mode Select SSI Receive Data Register SSI Receive Data Register Full SSI Receive Enable SSI Receive Interrupt Enable SSI Receive Shift Register SSI Status Register SSI Time Slot Register SSI Transmit Data Register SSI Transmit Data Register Empty SSI Transmit Enable SSI Transmit Interrupt Enable SSI Transmit Shift Register SSISR SSL Stack Pointer Register Stanislav Opichal Stanislav Opichal Za vodojemem 8 Olomouc 779 00 Czech Republic E-mail: Opichals@risc.upol.cz WWW: http://www.inf.upol.cz/~opichals/ Status Register STOP Stop Delay SUB SUBL SUBR SWI Synchronous Serial Interface System Stack T T Tcc TDE TE TFR TFS TIE Trace Transmit Frame Sync Flag Transmitter Underrun Error Flag TSR TST TUE TX U U U UF Unnormalized V V W WAIT WL0 WL1 Word Length Control X X X0 X1 X: X:R X:Y Y Y Y0 Y1 Y: Z Z Zero