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Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
@width      : 100
View Ref-FileTFR                     Transfer Data ALU Register

Operation:
    S -> D              (parallel move)

Assembler Syntax:
    TFR S,D             (parallel move)

Description:
    Transfer data from the specified source data ALU register S to the
specified destination data ALU accumulator D. TFR uses the internal data
ALU data paths; thus, data DO NOT pass through the data shifter/limiters.
This allows the full 56-bit contents of one of the accumulatorsto be
transferred into the other accumulator WITHOUT data shifting and/or
limiting. Moreover, since TFR uses the internal data ALU data paths,
parallel moves are possible. The TFR instruction only affects the L
condition code bit, wich can be set by data limiting associated with the
instruction's parallel move operations.

Example:
    TFR A,B A,X1    Y:((R4+N4),Y0   ;move A to B and X1, update Y0

    Before Execution:
    A  = $01:234567:89ABCD
    B  = $FF:FFFFFF:FFFFFF

    After Execution:
    A  = $01:234567:89ABCD
    B  = $01:234567:89ABCD

Explanation of Example:
    Prior to execution, the 56-bit A accumulator contains the value
$01:234567:89ABCD, and the 56-bit B accumulator contains the value
$FF:FFFFFF:FFFFFF. The execution of the TFR A,B instruction moves the
56-bit value in the A accumulator into the 56-bit B accumulator using
the internal data ALU data paths without any data shifting and/or limiting.
The value in the B accumulator WOULD have been limited if a MOVE A,B
instruction had been used. Note, however, that the parallel move portion
of the TFR instruction DOES use the data shifter/limiter. Thus, the value
stored in the 24-bit X1 register (not shown) WOULD have been limited in
this example. This instruction illustrate a TRIPLE move instruction.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting has occured during parallel move

Instruction Format:
    TFR S,D

    S = (A,B,X0,Y0,X1,Y1)
    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words