Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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View Ref-FileMode Register (MR) SR Bits: 15-8

The MR is a special-purpose control register defining the current
system state of the processor. The MR bits are affected by processor
reset, exception processing, the DO, end current DO loop (ENDDO),
return from interrupt (RTI), and SWI instructions and by instructions
that directly reference the MR register - OR immediate to control
register (ORI) and AND immediate to control register (ANDI). During
processor reset, the interrupt mask bits of the MR will be set; the
scaling mode bits, loop flag, and trace bit will be cleared.

INTERRUPT MASKS (BITS 8 AND 9):
    The interrupt mask bits, I1 and I0 reflect the current IPL of
 the processor and indicate the IPL needed for an interrupt source to
 interrupt the processor. The current IPL of the processor can be changed
 under software control. The interrupt mask bits are set during hardware
 reset but not during software reset.

    +----+----+---------------------+------------------+
    | I1 | I0 | Exception Permitted | Exception Masked |
    +----+----+---------------------+------------------+
    |  0 |  0 | IPL 0,1,2,3         | None             |
    +----+----+---------------------+------------------+
    |  0 |  1 | IPL 1,2,3           | IPL 0            |
    +----+----+---------------------+------------------+
    |  1 |  0 | IPL 2,3             | IPL 0,1          |
    +----+----+---------------------+------------------+
    |  1 |  1 | IPL 3               | IPL 0,1,2        |
    +----+----+---------------------+------------------+

SCALE MODE (BITS 10 AND 11):
    The scaling mode bits, S1 and S0,
specify the scaling to be performed in the data ALU shifter/limiter and
the rounding position in the data ALU multiply accumulator (MAC). The
scaling modes are shown in the following table:

    +----+----+--------------+-------------------------------------------+
    | S1 | S0 | Rounding Bit | Scaling Mode                              |
    +----+----+--------------+-------------------------------------------+
    |  0 |  0 |           23 | No Scaling                                |
    +----+----+--------------+-------------------------------------------+
    |  0 |  1 |           24 | Scale Down (1-Bit Arithmetic Right Shift) |
    +----+----+--------------+-------------------------------------------+
    |  1 |  0 |           22 | Scale Up (1-Bit Arithmetic Left Shift)    |
    +----+----+--------------+-------------------------------------------+
    |  1 |  1 |           -- | Reserved for Future Expansion             |
    +----+----+--------------+-------------------------------------------+

The shifter/limiter scaling mode affects data read from the A or B
accumulator registers out to the XDB and YDB. Different scaling modes
can be used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point
arithmetic. The scaling mode also affects the MAC rounding position
to maintain proper rounding when different portions of the accumulator
registers are read out of the XDB and YDB. The scaling mode bits, which
are cleared at the start of a long interrupt service routine, are also
cleared during a processor reset.

TRACE MODE (BIT 13):
    The trace mode T bit is specifies the tracing
function of the DSP. If the T bit is set at the begining of any
instruction execution, a trace exception will be generated after the
instruction execution is completed. If the T bit is cleared, tracing is
disabled and instruction instruction execution proceeds normally. If a
long interrupt is executed during a trace exception, the SR having the
trace bit set will will be staked, and the trace bit in the SR is
cleared. The T bit is also cleared during processor reset.

RESERVED STATUS (BITS 7,12,14):
    These bits, which are reserved for
future expansion, will read as zero during DSP read operations.

LOOP FLAG (BIT 15):
    The loop flag LF bit, set when a program loop is
is in progress, enables the detection of the end of a program loop. The
LF is the only SR bit that is restored when terminating a program loop.
Stacking and restoring the LF when initiating and exiting a program
loop, respectively, allow the nesting of program loops. At the start of
a long interrupt service routine, the SR (including the LF) is pushed
on the SS and the SR LF is cleared. When returning from the long
interrupt with an RTI instruction, the SS is restored. During a 
processor reset, the LF is cleared.