Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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@options    : -i +y +z -t4
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View Ref-FileSTOP                        Stop Instruction Processing

Operation:
    Enter the STOP processing state and stop the clock oscillator

Assembler Syntax:
    STOP

Description:
    Enter the STOP processing state. All activity in the processor is
suspended until the RESET or IRQA pin is asserted. The clock escillator
is gated off internally. The STOP processing state is a low-power standby
state.

    During the STOP state, port A is in an idle state with the control
signals held inactive (I.E., RD=WR=VCC etc.), the data pins (D0-D23) are
high impedance, and the address pins (A1-A15) are unchanged from the
previous instruction. If the bus grant was asserted when the STOP
instruction was executed, port A will remain three-stated until the
DSP exits the STOP state.

    If the exit from the STOP state was caused by a low level on the
RESET pin, then the processor will enter the reset processing state.
The time to recover from the STOP state using RESET will depend on the
oscillator used.

    If the exit from the STOP state was caused by a low level on the IRQA
pin, then the processor will service the highest priority pending interrupt
and will not service the IRQA interrupt unless it is highest priority. The
interrupt will be serviced after an internal delay counter counts 65,536
clock cycles (or a three clock cycle delay if the stop delay bit in the
OMR is set to one) plus 17T. During this clock stabilization count delay,
all peripherals and external interrupts are cleared and
re-enabled/arbitrated at the start of the 17T period following the count
interval. The processor will resume program execution at the instruction
following the STOP instruction that caused the entry into the STOP state
after the delay count plus 17T. If the IRQA pin is asserted when the STOP
instruction is executed, the clock will not be gated off, and the internal
delay counter will be started.

Restrictions:
    A STOP instruction cannot be used in a fast interrupt routine.
    A STOP instruction cannot be the last instruction in a DO loop (at LA).
    A STOP instruction cannot be repeated using REP instruction.

Condition Codes:
    The condition codes are not affected by this instruction.

Instruction Format:
    STOP

Timing:     The STOP instruction disable the internal clock oscillator
and internal distribution of the external clock.

Memory:     1 program word