Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
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View Ref-FileREP                     Repeat Next Instruction

Operation:
    LC -> TEMP; X:<ea> -> LC or
    LC -> TEMP; X:<aa> -> LC or
    LC -> TEMP; Y:<ea> -> LC or
    LC -> TEMP; Y:<aa> -> LC or
    LC -> TEMP; S -> LC      or
    LC -> TEMP; #xxx -> LC

    Repeat next instruction until LC=1
    TEMP -> LC

Assembler syntax:
    REP X:<ea>
    REP X:<aa>
    REP Y:<ea>
    REP Y:<aa>
    REP S
    REP #xxx

Description:
    Repeat the SINGLE-WORD INSTRUCTION immediately following the REP
instruction the specified number of times. The value specifying the
number of times the given instruction is to be repeated is loaded into
the 16-bit loop counter LC register. The single-word instruction is
then executed the specified number of times, decrementing the loop counter
(LC) after each execution until LC=1. When the REP instruction is in effect,
the repeated instruction is fetched only one time, and it remains in the
instruction register for the duration of the loop count. Thus, THE REP
INSTRUCTION IS NOT INTERRUPTIBLE (sequential repeats are also not
interruptible). The current loop counter (LC) value is stored in an internal
temporary register. If LC is set equal to zero, the instruction is repeated
65,536 times. The instruction's effective address specifies the address of
the value wich is to be loaded into the loop counter (LC). All address
register indirect adressing modes may be used. The absolute short and the
immediate short addressing modes may also be used. The four MS bits of the
12-bit immediate value are zeroed to form the 16-bit value that is to be
loaded into the loop counter (LC).

    If the A or B accumulator is specified as a SOURCE operand, the
accumulator value is optionally shifted according to the scaling mode bits
S0 and S1 in the system status register (SR). If the data out the shifter
indicates that the accumulator extension is in use, the value to be loaded
into the loop counter (LC) register will be limited to a 24-bit maximum
positive or negative saturation constant to minimize the error due to
truncation. The LS 16 bits of the resulting 24-bit value are then stored
in the 16-bit loop counter (LC) register.

    If the system stack register SSH is specified as a source operand, the
system stack pointer SP is postdecremented by 1 after SSH has been read.

Restrictions:
    The REP instruction can repeat any single-word instruction except the REP
instruction itself and any instruction that changes program flow. The
following instructions are not allowed to follow an REP instruction:

IMMEDIATELY AFTER REP

    DO          JSSET
    Jcc         REP
    JCLR        RTI
    JMP         RTS
    JSET        STOP
    JScc        SWI
    JSCLR       WAIT
    JSR

    Also a REP instruction cannot be the LAST instruction in a DO loop
(at LA). The assembler will generate an error if any of the previous
instructions are found immediately following an REP instruction.

Example:
REP X0                  ;repeat (X0) times
MAC X1,Y1,A X:(R1)+,X1 Y:(R4)+,Y1   ;X1*Y1+A -> A, update X1,Y1

Before execution:
    X0 = $000100
    LC = $0000

After execution:
    X0 = $000100
    LC = $0100

Explanation of example:
    Prior to execution, the 24-bit X0 register contains the value $000100,
and the 16-bit loop counter (LC) register contains the value $0000. The
execution of the REP X0 instruction takes the 24-bit value in the X0
register, truncates the MS 8 bits, and stores the 16 LS bits in the 16-bit
loop counter (LC) register. Thus, the single-word MAC instruction
immediately following the REP instruction is repeated $100 times.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting occured using A or B as source operands

Instruction format:
    REP X:<ea>
    REP X:<aa>
    REP Y:<ea>
    REP Y:<aa>
    REP S
    REP #xxx

    ea = (Rn)-Nn
         (Rn)+Nn
         (Rn)-
         (Rn)+
         (Rn)
         (Rn+Nn)
         -(Rn)

    aa = 6-bit Absolute Short Address

    #xxx = 12-bit Immediate Short Data

    S = (X0,Y0,X1,Y1,A2,A1,A0,B2,B1,B0,A,B,R0-R7
         N0-N7,M0-M7,SR,OMR,SP,SSH,SSL,LA,LC)

Timing:     4 oscillator clock cycles

Memory:     1 program word