Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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View Ref-FileNORM                        Normalize Accumulator Iteration

Operation:
    If  ~E & U & ~Z = 1, then ASL D and Rn-1 -> Rn
    else if         E = 1, then ASR D and Rn+1 -> Rn
    else NOP

    where
    ~ denotes the logical complement
    & denotes the logical AND operator

Assembler Syntax:
    NORM    Rn,D

Description:
    Perform one normalization iteration on the specified destination operand
D, update the specified address register Rn based upon the result of that
iteration, and store the result back in the destination accumulator. This
is a 56-bit operation. If the accumulator extension is not in use, the
accumulator is unnormalized, and the accumulator is not zero, the
destination operand is arithmetically shifted one bit to the left, and the
specified address register is decremented by 1. If the accumulator extension
is in use, the destination operand is arithmetically shifted one bit to the
right, and the specified address register is incremented by 1. If the
accumulator is normalized, or zero, a NOP is executed and the specified
address register is not affectred. Since the operation of the NORM
instruction depends on the E, U and Z condition code register bits, these
bits must correctly reflect the current state of the destination accumulator
prior to executing the NORM instruction. Note that the L and V bits in the
condition code register will be cleared unless they have been improperly
set up prior to executing the NORM instruction.

Example:
    REP #$2E        ;maximum number of iterations needed
    NORM    R3,A        ;perform 1 normalization iteration

Before Execution:
    A  = $00:000000:000001
    R3 = $0000

After Execution:
    A  = $00:400000:000000
    R3  $FFD2

Explanation of Example:
    Prior to execution, the 56-bit A accumulator contains the value
$00:000000:000001, and the 16-bit R3 address register contains the value
$0000. The repetition of the NORM R3,A instruction normalizes the value
in the 56-bit accumulator and stores the resulting number of shifts
performed during that normalization process in the R3 address register.
A negative value reflects the number of left shifts performed; a positive
number reflects the number of right shifts performed during the
normalization process.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if overflow has occured in A or B result
    E- Set if the signed integer portion of A or B result is in use
    U- Set if A or B result is unnormalized
    N- Set if bit 55 of A or B result is set
    Z- Set if A or B result equals zero
    V- Set if bit 55 is changed as a result of a left shift

Instruction Format:
    NORM    Rn,D

Timing:     2 oscillator clock cycles

Memory:     1 program words