Topic : MC56001 Documentation Author : JAY Software Version : 1.0 (19/11/1997) Subject : Programming/Assembler Nodes : 152 Index Size : 4106 HCP-Version : 4 Compiled on : Atari @charset : atarist @lang : @default : @help : @options : -i +y +z -t4 @width : 100 View Ref-FileMOVEC Move Control Register Operation: Assembler Syntax: X:ea->D1 MOVEC X:ea,D1 X:aa->D1 MOVEC X:aa,D1 S1->X:ea MOVEC S1,X:ea S1->X:aa MOVEC S1,X:aa Y:ea->D1 MOVEC Y:ea,D1 Y:aa->D1 MOVEC Y:aa,D1 S1->Y:ea MOVEC S1,Y:ea S1->Y:aa MOVEC S1,Y:aa S1->D2 MOVEC S1,D2 S2->D1 MOVEC S2,D1 #xxxx->D1 MOVEC #xxxx,D1 #xx->D1 MOVEC #xx,D1 Description: Move the contents of the specified source control register S1 or S2 to the specified destination or move the specified source to the specified destination control register D1 or D2. The control registers S1 and D1 are subset of the S2 and D2 register set and consist of the address ALU modifier registers and the program controller registers. These registers. These registers may be moved to or from any other register or memory space. All memory addressing modes, as well as an immediate short addressing mode, may be used. If the system stack register SSH is specified as a source operand, the system stack pointer (SP) is postdecremented by 1 after SSH has been read. If the system stack register SSH is specified as a destination operand, the system stack pointer (SP) is preincremented by 1 before SSH is written. This allows the system stack to be efficiently extended using software stack pointer operations. When a 56-bit accumulator (A or B) is specified as a source operand, the accumulator value is optionnaly shifted according to the scaling mode bits S0 and S1 in the system status register (SR). If the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24-bit destination, the value stored in the destination is limited to a maximum positive or negative saturation constant to minimize truncation error. If the data is to be moved into 16-bit destination and the accumulator extension register is in use, the value is limited to a maximum positive or negative saturation constant whose LS 16 bits are then stored in the 16-bit destination register. Limiting does not occur if an individual 24-bit accumulator register (A1,A0,B1, or B0) is specified as a source operand instead of the full 56-bit accumulator (A or B). This limiting features allows block floating-point operations to be performed with error detection since the L bit in the condition code register is latched. When a 56-bit accumulator (A or B) is specified as a destination operand, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the MS bits ofthe source operand (bit 23) and appending the source operand with 24 LS zeros. Whenever a 16-bit source operands is to be moved into a 24-bit destination, the 16-bit value is stored in the 16 LS 16 bits of the 24-bit destination, and the MS 8 bits of that destination are zeroed. Similary, whenever a 16-bit source operand is to be moved into a 56-bit accumulator, the 16-bit value is moved into the LS 16 bits of the MSP portion of the accumulator (A1 or B1), the MS 8 bits of the MSP portion of that accumulator are zeroed, and the resulting 24-bit value is extended to 56 bits by sign extending the MS bit and appending the result with 24 LS zeros. Note that for 24-bit source operands both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (A1 or B1). NOTE: Due to pipelining, if an address register (R,N, or M) is changed using a move-type instruction, the new contents of the destination address register will not beavailable for use during the following instruction (i.e., there is a single instruction cycle pipeline delay). Restrictions: NOTE: The following restrictions represent very unusual operations, which probably would never be used but are listed only for completeness. A MOVEC instruction used within a DO loop which specifies SSH as the source operand or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA-2, LA-1, or LA within that DO loop. A MOVEC instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEC instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction. A MOVEC instruction which specifies SSH as the source operand or SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an RTI instruction. A MOVEC instruction which specifies SSH as the source operand or SSH, SSL, or SP as the destination operand cannot be used immediately before an RTS instruction. A MOVEC instruction which specifies SP as the destination operand cannot be used immediately before a MOVEC, MOVEM, or MOVEP instruction which specifies SSH or SSL as the source operand. A MOVEC SSH,SSH instruction is illegal and cannot be used. Example: MOVEC LC,X0 ;move LC into X0 Before Execution: LC = $0100 X0 = $123456 After Execution: LC = $0100 X0 = $000100 Explanation of Example: Prior to execution, the 16-bit loop couter (LC) register contains the value $0100, and the 24-bit X0 register contains the value $123456. The execution of the MOVEC LC,X0 instruction moves the contents of the 16-bit LC register into the 16 LS bits of the 24-bit X0 register and zeros the 8 MS bits of the X0 register. Condition Codes: 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |<- MR ->|<- CCR ->| For D1 or D2 = SR operand: L- Set according to bit 6 of the source operand E- Set according to bit 5 of the source operand U- Set according to bit 4 of the source operand N- Set according to bit 3 of the source operand Z- Set according to bit 2 of the source operand V- Set according to bit 1 of the source operand C- Set according to bit 0 of the source operand For D1 and D2 != SR operand: L- Set if data limiting has occured during move Instruction Format: MOVEC X:ea,D1 MOVEC X:aa,D1 MOVEC S1,X:ea MOVEC S1,X:aa MOVEC Y:ea,D1 MOVEC Y:aa,D1 MOVEC S1,Y:ea MOVEC S1,Y:aa MOVEC S1,D2 MOVEC S2,D1 MOVEC #xxxx,D1 MOVEC #xx,D1 #xxxx = Immediate Data #xx = 8-bit Immediate Short Data aa = 6-bit Absolute Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address S1 = (Mn,SR,OMR,SP,SSH,SSL,LA,LC) D1 = (Mn,SR,OMR,SP,SSH,SSL,LA,LC) S2 = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR, OMR,SP,SSH,SSL,LA,LC) D2 = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR, OMR,SP,SSH,SSL,LA,LC) Timing: 2 + mvc oscillator clock cycles Memory: 1 + ea program words