Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
@width      : 100
View Ref-FileX:Y                     X Y Memory Data Move

Operation:                          Assembler Syntax:
    (...);X:<eax>->D1;Y:<eay>->D2       (...) X:<eax>,D1 Y:<eay>,D2
    (...);X:<eax>->D1;S2->Y:<eay>       (...) X:<eax>,D1 S2,Y:<eay>
    (...);S1->X:<eax>;Y:<eay>->D2       (...) S1,X:<eax> Y:<eay>,D2
    (...);S1->X:<eax>;S2->Y:<eay>       (...) S1,X:<eax> S2,Y:<eay>

Description:
    Move one-word operand from/to X memory and move another word
operand from/to Y memory. Note that two independent effective addresses
are specified (<eax> and <eay>) where one of the effective addresses
uses the lower bank of address registers (R0-R3) while the other
effective address uses the upper bank of address registers (R4-R7).
All parallel addressing modes may be used.

    If the arithmetic or logical opcode-operand portion of the instruction
specifies a given destination accumulator, that same accumulator or
portion of that accumulator may not be specified as a destination D1
or D2 in the parallel data bus move operation. Thus, if the
opcode-operand portion of the instruction specifies the 56-bit A
accumulator as its destination, the parallel data bus move portion of
the instruction may not specify A as its destination D1 or D2.
Similary, if the opcode-operand portion of the instruction specifies
the  56-bit B accumulator as its destination, the parallel data bus
move portion of the instruction may not specify B as its destination
D1 or D2. That is, duplicate destinations are NOT allowed within the
same instruction. D1 and D2 may not specify the same register.

    If the opcode-operand portion of the instruction specifies a given
source or destination register, that same register or portion of that
register may be used as a source S1 and/or S2 in the parallel data bus
move operation. This allows data to be moved in the same instruction in
which it is being used as a source operand by data ALU operation. That
is, duplicate sources are allowed within the same instruction. Note
that S1 and S2 may specify the same register.

Example:
    MPYR X1,Y0,A X1,X:(R0)+ Y0,Y:(R4)+N4    ;X1*Y0->A, save X1 and Y0

    Before Execution:
        X1      = $123123
        Y0      = $456456
        R0      = $1000
        R4      = $0100
        N4      = $0023
        X:$1000 = $000000
        Y:$0100 = $000000

    After Execution:
        X1      = $123123
        Y0      = $456456
        R0      = $1001
        R4      = $0123
        N4      = $0023
        X:$1000 = $123123
        Y:$0100 = $456456

Explanation of example:
    Prior to execution, the 24-bit X1 register contains the value
$123123, the 24-bit Y0 register contains the value $456456, the 16-bit
R0 address register contains the value $1000, the 16-bit R4 address
register contains the value $0100, the 16-bit N4 address offset
register contains the value $000000, the 24-bit X memory location
X:$1000 contains the value $000000, and the 24-bit Y memory location
Y:$0100 contains the value $000000. The execution of the parallel move
portion of the instruction, X1,X:(R0)+ Y0,Y:(R4)+N4, moves the 24-bit
value in the X1 register into the 24-bit X memory location X:$1000
using the 16-bit R0 address register, moves the 24-bit value in the Y0
register into the 24-bit Y memory location Y:$0100 using the 16-bit R4
address register, updates the 16-bit value in the R0 address register,
and updates the 16-bit R4 address register using the 16-bit value in
the R0 address register, and updates the 16-bit R4 address register
using the 16-bit N4 address offset register. The contents of the N4
address offset register are not affected.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting has occured during parallel move

NOTE: The MOVE A,X:<eax> B,Y:<eay> operation will result in one or
two 24-bit positive and/or negative saturation constant(s) being
stored in the specified 24-bit X and/or Y memory locations if the
signed integer portion of the A and/or B accumulator(s) is in use.

Instruction Format:
    (...) X:<eax>,D1 Y:<eay>,D2
    (...) X:<eax>,D1 S2,Y:<eay>
    (...) S1,X:<eax> Y:<eay>,D2
    (...) S1,X:<eax> S2,Y:<eay>

    eax = (Rn)+Nn
          (Rn)-
          (Rn)+
          (Rn)

    eay = (Rn)+Nn
          (Rn)-
          (Rn)+
          (Rn)

    S1 = (X0,X1,A,B)
    D1 = (X0,X1,A,B)

    S2 = (Y0,Y1,A,B)
    D2 = (Y0,Y1,A,B)

Timing:     mv oscillator clock cycles

Memory:     mv program words