Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i +y +z -t4
@width      : 100
View Ref-FileY:                      Y Memory Data Move

Operation:                      Assembler Syntax:
    (.....); Y:ea->D                (.....) Y:ea,D
    (.....); Y:aa->D                (.....) Y:aa,D
    (.....); S->Y:ea                (.....) S,Y:ea
    (.....); S->Y:aa                (.....) S,Y:aa
    (.....); #xxxxxx->D             (.....) #xxxxxx,D

Description:
    Move the specified word operand from/to Y memory. All memory
addressing modes, including absolute addressing and 24-bit immediate
data, may be used. Absolute short addressing may also be used.

    If the arithmetic or logical opcode-operand portion of the instruction
specifies a given destination accumulator, that same accumulator or
portion of that accumulator may notbe specified as destination D in
the parallel data bus move operation. Thus, if the opcode-operand
portion of the instruction specifies the 56-bit A accumulator as its
destination, the parallel data bus move portion of the instruction may
not specify A0,A1,A2, or A as its destination D. Similary, if the
opcode-operand portion of the instruction specifies the 56-bit B
accumulator as its destination, the parallel data bus move portion of
the instruction may not specify B0,B1,B2, or B as its destination D.
That is, duplicate destinations are NOT allowed within the same
instruction.

    If the opcode-operand portion of the instruction specifies a given
source or destination register, that same register or portion of that
register may be used as a source S in the parallel data bus move
operation. This allows data to be moved in the same instruction in
which it is being used as a source operand by data ALU operation.
That is, duplicate sources are allowed within the same instruction.

    When a 24-bit source operand is moved ino a 16-bit destination
register, the 16 LS bits of the 24-bit source operand are stored in
the 16-bit destination register. When a 16-bit source operand is moved
into a 24-bit destination register, the 16LS bits of the destination
register are loaded with the contents of the 16-bit source operand,
and the eight MS bits of the 24-bit destination register are zeroed.

NOTE: This parallel data move is considered to be a move-type
instruction. Due to pipelining, if an address register (R or N) is
changed using a move-type instruction, the new contents of the
destination address register will not be available for use during the
following instruction (i.e., there is a single instruction cycle
pipeline delay).

Example:
    EOR X0,B    #$123456,A  ;exclusive OR X0 and B, update A accumulator

    Before Execution:
        A = $FF:FFFFFF:FFFFFF

    After Execution:
        A = $00:123456:000000

Explanation of Example:
    Prior to execution, the 56-bit A accumulator contains the value
$FF:FFFFFF:FFFFFF. The execution of the parallel move portion of the
instruction, #$123456,A, moves the 24-bit immediate value $123456 into
the 24-bit A1 register, then sign extends that value into the A2
portion of the accumulator, and zeros the lower 24-bit A0 portion of
the accumulator.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-         MR        ->|<-       CCR         ->|

    L- Set if data limiting has occured during parallel move

NOTE: The MOVE A,Y:ea operation will result in a 24-bit positive or
negative saturation constant being stored in the specified 24-bit X
memory if the signed integer portion of the A accumulator is in use.

Instruction Format:
    (.....) Y:ea,D
    (.....) S,Y:ea
    (.....) #xxxxxx,D
    (.....) Y:aa,D
    (.....) S,Y:aa

    #xxxxxx = 24-bit Immediate Data

    aa = 6-bit Absolute Short Address

    ea = (Rn)-Nn
         (Rn)+Nn
         (Rn)-
         (Rn)+
         (Rn+Nn)
         -(Rn)
         Absolute address

    S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn)
    D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn)

Timing:     mv oscillator clock cycles

Memory:     mv program words