Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
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View Ref-FileR                       Register to Register Data Move

Operation:
    (.....);S->D

Assembler Syntax:
    (.....) S,D

Description:
    Move the source register S to the destination register D.

    If the arithmetic or logical opcode_operand portion of the instruction
specifies a given destination accumulator, that same accumulator or
portion of that accumulator may not be specified as a destination D in
the parallel data bus move operation. Thus, if the opcode-operand
portion of the instruction specifies the 56-bit A accumulator as its
destination, the parallel data bus move portion of the instruction
may not specify A0, A1, A2, or A as its destination D. Similary, if the
opcode-operand portion of the instruction specifies the 56-bit B
accumulator as its destination, the parallel data bus move portion of
the instruction may not specify B0,B1,B2, or B as its destination D.
That is, duplicate destination are NOT allowed within the same
instruction.

    If the opcode-operand portion of the instruction specifies a given
source or destination register, that same register or portion of that
register may be used as a source S in the parallel data bus move
operation. This allows data to be moved in the same instruction in
which it is being used as a source operand by a data ALU operation.
That is, duplicate sources are allowed within the same instruction.

    When a 24-bit source operand is moved into a 16-bit destination
register, the 16 LS bits of the 24-bit source operand are stored in
16-bit destination register. When a 16-bit source operand is moved into
a 24-bit destination register, the 16 LS bits of the destination
register are loaded with the contents of the 16-bit source operand,
and the eight MS bits of the 24-bit destination register are zeroed.

NOTE: The MOVE A,B operation will result in a 24-bit positive or
negative saturation constant being stored in the B1 portion of the B
accumulator if the signed integer portion of the A accumulator is in
use.

NOTE: This parallel data move is considered to be a move-type
instruction. Due to pipelining, if an address register (R or N) is
changed using a move-type instruction, the new contents of the
destination address register will not be available for use during the
following instruction (i.e., there is a single instruction cycle
pipeline delay).

Example:
    MACR    -X0,Y0,A    Y1,N5   ;-X0*Y0+A->A, move Y1->N5

    Before execution:
        Y1 = $001234
        N5 = $0000

    After execution:
        Y1 = $001234
        N5 = $1234

Explanation of Example:
    Prior to execution, the 24-bit Y1 register contains the value
$001234 and the 16-bit address offset register N5 contains the value
$0000. The execution of the parallel move portion of the instruction,
Y1,N5, moves the 16 LS bits of the 24-bit value in the Y1 register into
the 16-bit N5 register.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting has occured during parallel move

Instruction Format:
    (.....) S,D

    S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn)
    D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn)

Timing:     mv oscillator clock cycles

Memory:     mv program words