Topic       : MC56001 Documentation
Author      : JAY Software
Version     : 1.0 (19/11/1997)
Subject     : Programming/Assembler
Nodes       : 152
Index Size  : 4106
HCP-Version : 4
Compiled on : Atari
@charset    : atarist
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View Ref-FileLSL                     Logical Shift Left

Operation:

             47        24
            +------------+
        C <-|<-----------|<- 0 (parallel move)
            +------------+

Assembler Syntax:
    LSL D               (parallel move)

Description:
    Logical shifts bits 47-24 of the destination operand D one bit to
the left and store the result in the destination accumulator. Prior to
instruction execution, bit 47 of D is shifted into the carry bit C,
and zero is shifted into bit 24 of the destination accumulator D. This
instruction is a 24-bit operation. The remainig bits of the
destination operand E are not affected. If zero shift count is
specified, the carry bit is cleared. The difference between LSL and ASL
is that LSL operates on only A1 or B1 and always clears the V bit.

Example:
    LSL B   #$7F,R0     ;shift B1 one bit to the left, set up R0

    Before execution:
        B  = $00:F01234:13579B
        SR = $0300

    After execution:
        B  = $00:E02468:13579B
        SR = $0309
 
Explanation of Example:
    Prior to execution, the 56-bit B accumulator contains the value
$00:F01234:13579B. The execution of the LSL B instruction shifts the
24-bit value in the B1 register one bit to the left and stores the
result back in the B1 register.

Condition Codes:

     15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |LF|**| T|**|S1|S0|I1|I0|**| L| E| U| N| Z| V| C|
    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    |<-           MR         ->|<-       CCR      ->|

    L- Set if data limiting has occured during parallel move
    N- Set if bit 47 of A or B result is set
    Z- Set if bits 47-24 of A or B result are zero
    V- Always cleared
    C- Set if bit 47 of A or B was set prior to instruction execution

Instruction Format:
    LSL D

    D = (A,B)

Timing:     2 + mv oscillator clock cycles

Memory:     1 + mv program words